Services and Expertise

  • Interact closely with Architecture team for setting up the STA environment.

  • Constraints Generations.

  • Time-proven project planning methodology.

  • Give Valuable feedback to Floorplan team for IO and macro placement.

  • Looking deep into clock and reset architecture.

  • Look for integration issue ,if any.

  • On fly debugging for constraint updating.

  • Decide on margins/derates/skew/ latency based on stage of design.

  • Give full support to Synthesis Team for achieving a high quality netlist , in terms of timing.

  • Work Closely with PD team for CTS and timing closure.

  • Identifying various STA modes required for covering complete functionality and testing of SOC.

  • Timing Analysis across all corners,all modes.

  • Timing closure in backend tool, with appropriate margins.

s3
  • Android based / Web based product development.

  • IOT product development.

  • Microcontroller based product development.

  • FPGA based products.

  • Testing

  • DSP based products.

  • Image sensor development.

  • GPS, GPRS based product development.

s2
  • Time-proven project planning methodology.

  • Expertise in Verification of Core Processor : ARM -11, Cold Fire.

  • Development of module-level verification environment that is portable to chip level.

  • Efficiency in directed and constraints-driven random verification to achieve coverage.

  • Development of reusable verification environment at module and chip level.

  • Understanding product requirements and specifications.

  • RTL Coding, Simulation.

  • Developing Micro Architecture Document, HLD and LLD.

  • Automation at both module and system level to reduce manual effort.

  • Reuse of embedded assertions to achieve maximum coverage.

  • Mixed-mode verification using Specman-e, Vera, C/C++, Metlab, Verilog/VHDL, assembly and assertions.

  • Expertise in understanding and helping STA environment.

  • GLS � Our USP full custom level GLS run.

  • Help in understanding and RTL Implementation of DFT.

  • Large resource pool with domain expertise in various standards, protocols and embedded processors.

  • Memory from 28 nm, 45nm.

  • Analog blocks such as OPAM, Band gap , Voltage regulator Oscillator PLL , Buffer ( Analog Layout ).

  • VCO and amplifiers.

  • Data Converter.

  • SRAM & DRAM Custom layout Design.

  • Power Management.

  • Cell Library Development & IO�s Layout at various specification.

  • Full Chip , full custom design.

s3
  • Successful project planning/execution methodology.

  • Floorplanning : Pad/Macro placement, powerplanning.

  • Library and hard macro sanity check.

  • Timing/Congestion aware Floorplanning/Placement.

  • CTS with clustering the root cells for better insertion delay and skew reduction.

  • Reset tree building/Data skew balancing/Hand made routing on special nets based on requirement.

  • Complete sign-off checks including IR drop analysis,DRC/LVS,EM, Timing, LEC to have a successful first pass silicon.

  • Experience from 180nm to 14nm technological nodes.

  • Around 6 chips on volume production.