Semiconductor Domain


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Architecture and Design Expertise

    uArch Specification to Net list

    Chip planning, interface details and detailed micro architecture for all PD modules.

    Experience in leading and implementing complex algorithmic designs.

    Designed chip up to 16FF technology with more than 12M instances and up to 512Mb embedded memory.

    Experience in designing for timing closure friendly for speed up to 1.2GHz.

    Ethernet and Interlaken Phy and MAC designs.

    PCIe implementation up to Gen4 and 16-lanes supporting 1, 2 or 4 ports

    Up to 48 56G PAM4 serdes integration.

    AVS and power islands for power saving.

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Design Verification Expertise

    SoC, ASIC Full-chip, Sub-system and IP level Verification

    Mixed-language verification using SystemVerilog, Specman-e, Vera, C/C++, Verilog/VHDL OVM, VMM and UVM based environment

    VIP/BFMs, Protocol monitors and checkers

    Architecture models in C / System Verilog

    Directed & Constrained Random verification

    Functional coverage driven verification

    Code coverage analysis

    Assertion based formal verification

    Low Power Design verification

    Gate Level Simulations

    Formal Verification

    Emulations using Palladium / Z1

    Chip bringup and ATE Vector Generation & Support

DFT Expertise

    Mentor Tessent/Synopsys DFT compiler for hierarchical scan insertion

    Option to insert membist in RTL or netlist

    BISR chain for auto loading all needed redundancy and configuration from OTP/Efuse

    At-speed scan and LBIST to cover more than 99% of logic

    Extensive experience in bringing up chip in ATE and support till production including HTOL, ESD, functional validation in the lab.

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Physical Design Implementation Expertise

PD implementation

    Floor planning

    Place and Route


    STA & Design Analysis

      Constraint Generation


      Timing Sign of

      Xtalk, Noise ,Signal integrity

      AOCV and POCV

      Physical Verification & DFM

        LVS,DRC,EEC,ESD, Antenna

        OPC,CMP, Yield etc

Analog & Mixed Siganal Layout Expertise

    Exposure to multiple technology nodes, 130u to 16nm.

    Chip planning, interface details and detailed micro architecture for all PD modules.

    Floor planning Transistor & Block level layout, Power planning, critical signals interaction at block, IP & chip level. .

    Bump and ESD planning.

    EMIR, thermal aware EMIR, DFM, Density, Client specific custom rules and support to PD/chip level issues.

    Efficiency of layout to minimize effort/man hours. (ex: reuse of blocks to make use in both NS and EW orientations)

    Distribution of tasks and supervising delivering best quality by having timely reviews with clients.

    Post layout support.

    Creation of test benches for simulations to reduce dependency of layout completion and avoid convergence.

    Skill coding for productive layouts .

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