• Synthesis for hierarchical designs with zero-wireload and physical.
  • Static Timing Analysis for hierarchical designs for functional and test modes with timing DRC fixes.
  • Experience in low power design and signal integrity.
  • Conversant about timing closure in physical design and timing-ECO generation.
  • Should have experience with formal verification and power analysis flow.
  • Tools:
  • Synopsys: PrimeTime, Design Compiler Ultra, Formality, MVRC.
  • Interfaces :- PCIE*;Flash controllers (ONFI*);DDR2,3,4;GPIO.
  • Scripting using Tcl or Perl desirable.
  • Good Communication skills.